China Epitaxial Wafers Manufacturers, Suppliers, Factory

SiC substrate can have microscopic defects, such as Threading Screw Dislocation (TSD), Threading Edge Dislocation (TED), Base Plane Dislocation (BPD), and others. These defects are caused by deviations in the arrangement of atoms at the atomic level.

In the semiconductor industry, epitaxial layers play a crucial role by forming specific single-crystal thin films atop a wafer substrate, collectively known as epitaxial wafers. Particularly, silicon carbide (SiC) epitaxial layers grown on conductive SiC substrates produce homogenous SiC epitaxial wafers, which are instrumental in the fabrication of power devices such as Schottky diodes, MOSFETs, and IGBTs, with 4H-SiC substrates being the most widely utilized.

Defect-free epitaxial growth occurs when one crystal lattice has nearly identical lattice constants to another. Growth happens when lattice sites of the two lattices at the interface region are approximately matched, which is possible with a small lattice mismatch (less than 0.1%). This approximate matching is achieved even with elastic strain at the interface, where each atom is slightly displaced from its original position in the boundary layer. While a small amount of strain is tolerable for thin layers and even desirable for quantum well lasers, the strain energy stored in the crystal is generally lowered by the formation of misfit dislocations, which involve a missing row of atoms in one lattice.

Within the silicon carbide (SiC) industry chain, substrate suppliers hold significant leverage, primarily due to value distribution. SiC substrates account for 47% of the total value, followed by epitaxial layers at 23%, while device design and manufacturing constitute the remaining 30%. This inverted value chain stems from the high technological barriers inherent to substrate and epitaxial layer production. Three major challenges plague SiC substrate growth: stringent growth conditions, slow growth rates, and demanding crystallographic requirements. These complexities contribute to increased processing difficulty, ultimately resulting in low product yields and high costs. Furthermore, the epitaxial layer’s thickness and doping concentration are critical parameters directly impacting the final device performance.

Plasma Enhanced Chemical Vapor Deposition (PECVD) is a widely used technology in chip manufacturing. It utilizes the kinetic energy of electrons within plasma to activate chemical reactions in the gas phase, thereby achieving thin-film deposition.

The wafer notch is a V-shaped or U-shaped groove on the edge of a semiconductor wafer. Far from being a defect incurred during the manufacturing process, it is the critical structural marker that was intentionally designed, whose core function lies in enabling precise positioning and orientation identification of the wafer. Wafer flat was used as the orientation marking in the early stages of wafer technology development. However, as wafer sizes gradually increased, the flat-edge design occupied more effective area, thus being gradually replaced by the more compact notch.