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Japan recently restricted exports of 23 types of semiconductor manufacturing equipment. The announcement has sent ripples across the industry, as the move is expected to have a significant impact on global supply chains for semiconductor manufacturing.

Etching is an essential process in semiconductor manufacturing. This process can be categorized into two types: dry etching and wet etching. Each technique has its own advantages and limitations, making it crucial to understand the differences between them. So, how do you choose the best etching method? What are the pros and cons of dry etching and wet etching?

The first generation of semiconductor materials is mainly represented by silicon (Si) and germanium (Ge), which began to rise in the 1950s. Germanium was dominant in the early days and was mainly used in low-voltage, low-frequency, medium-power transistors and photodetectors, but due to its poor high temperature resistance and radiation resistance, it was gradually replaced by silicon devices in the late 1960s. Silicon is still the main semiconductor material in the field of microelectronics due to its high technological maturity and cost advantages.

Within the silicon carbide (SiC) industry chain, substrate suppliers hold significant leverage, primarily due to value distribution. SiC substrates account for 47% of the total value, followed by epitaxial layers at 23%, while device design and manufacturing constitute the remaining 30%. This inverted value chain stems from the high technological barriers inherent to substrate and epitaxial layer production. Three major challenges plague SiC substrate growth: stringent growth conditions, slow growth rates, and demanding crystallographic requirements. These complexities contribute to increased processing difficulty, ultimately resulting in low product yields and high costs. Furthermore, the epitaxial layer’s thickness and doping concentration are critical parameters directly impacting the final device performance.

The wafer notch is a V-shaped or U-shaped groove on the edge of a semiconductor wafer. Far from being a defect incurred during the manufacturing process, it is the critical structural marker that was intentionally designed, whose core function lies in enabling precise positioning and orientation identification of the wafer. Wafer flat was used as the orientation marking in the early stages of wafer technology development. However, as wafer sizes gradually increased, the flat-edge design occupied more effective area, thus being gradually replaced by the more compact notch.