China Silicon carbide Optical mirror Manufacturers, Suppliers, Factory

Taiwan's Power Semiconductor Manufacturing Corporation (PSMC) has announced plans to build a 300mm wafer fab in Japan in collaboration with SBI Holdings. The purpose of this collaboration is to strengthen Japan's domestic IC (integrated circuit) supply chain, with a particular focus on circuits for AI edge computing and packaging technologies.

In semiconductor fabrication, etching is one of the major steps, along with photolithography and thin-film deposition. It involves removing unwanted materials from the surface of a wafer using chemical or physical methods. This step is carried out after coating, photolithography, and developing. It is used to remove the exposed thin film material, leaving only the desired portion of the wafer, and then removing the excess photoresist. These steps are repeated numerous times to create complex integrated circuits.

As global acceptance of electric vehicles gradually increases, Silicon Carbide (SiC) will encounter novel growth opportunities in the forthcoming decade. It is anticipated that manufacturers of power semiconductors and operators in the automotive industry will participate more actively in the construction of this sector’s value chain.

The current third-generation semiconductors are primarily based on Silicon Carbide, with substrates accounting for 47% of device costs, and epitaxy accounting for 23%, totaling approximately 70% and forming the most crucial part of the SiC device manufacturing industry.

Within the silicon carbide (SiC) industry chain, substrate suppliers hold significant leverage, primarily due to value distribution. SiC substrates account for 47% of the total value, followed by epitaxial layers at 23%, while device design and manufacturing constitute the remaining 30%. This inverted value chain stems from the high technological barriers inherent to substrate and epitaxial layer production. Three major challenges plague SiC substrate growth: stringent growth conditions, slow growth rates, and demanding crystallographic requirements. These complexities contribute to increased processing difficulty, ultimately resulting in low product yields and high costs. Furthermore, the epitaxial layer’s thickness and doping concentration are critical parameters directly impacting the final device performance.

Gallium Nitride (GaN) epitaxial wafer growth is a complex process, often utilizing a two-step method. This method involves several critical stages, including high-temperature baking, buffer layer growth, recrystallization, and annealing. By meticulously controlling the temperature throughout these stages, the two-step growth method effectively prevents wafer warping caused by lattice mismatch or stress, making it the predominant fabrication method for GaN epitaxial wafers globally.