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Epitaxial wafer process is a critical technique used in semiconductor manufacturing. It involves the growth of a thin layer of crystal material on top of a substrate, which has the same crystal structure and orientation as the substrate. This process creates a high-quality interface between the two materials, allowing for the development of advanced electronic devices.

SiC substrate can have microscopic defects, such as Threading Screw Dislocation (TSD), Threading Edge Dislocation (TED), Base Plane Dislocation (BPD), and others. These defects are caused by deviations in the arrangement of atoms at the atomic level.

Epitaxial growth refers to the process of growing a crystallographically well-ordered monocrystalline layer on a substrate. Generally speaking, epitaxial growth involves the cultivation of a crystal layer on a single-crystal substrate, with the grown layer sharing the same crystallographic orientation as the original substrate. Epitaxy is extensively utilized in semiconductor manufacturing, such as the production of epitaxial silicon wafers in the integrated circuit industry.

The Silicon Carbide (SiC) production process encompasses the preparation of substrate and epitaxy from the materials side, followed by chip design and manufacturing, device packaging, and finally, distribution to downstream application markets. Among these stages, substrate material processing is the most challenging aspect of the SiC industry. SiC substrates are both hard and brittle, making cutting, grinding, and polishing extremely difficult. This increases the likelihood of defects during processing and reduces the yield rate. Currently, major international SiC manufacturers are planning to transition from 6-inch to 8-inch SiC wafers. Overcoming the challenges associated with 8-inch substrates has become a critical benchmark for the SiC industry. This article will introduce the key parameters of SiC substrates.

Defect-free epitaxial growth occurs when one crystal lattice has nearly identical lattice constants to another. Growth happens when lattice sites of the two lattices at the interface region are approximately matched, which is possible with a small lattice mismatch (less than 0.1%). This approximate matching is achieved even with elastic strain at the interface, where each atom is slightly displaced from its original position in the boundary layer. While a small amount of strain is tolerable for thin layers and even desirable for quantum well lasers, the strain energy stored in the crystal is generally lowered by the formation of misfit dislocations, which involve a missing row of atoms in one lattice.

Chemical Vapor Deposition (CVD) is a versatile thin-film deposition technique widely employed in the semiconductor industry for fabricating high-quality, conformal thin films on various substrates. This process involves chemical reactions of gaseous precursors onto a heated substrate surface, resulting in the formation of a solid thin film. This article delves into the intricacies of CVD, exploring its mechanisms, advantages, limitations, and key applications in semiconductor manufacturing.