China Silicon carbide ceramic tubes Manufacturers, Suppliers, Factory

SiC substrate can have microscopic defects, such as Threading Screw Dislocation (TSD), Threading Edge Dislocation (TED), Base Plane Dislocation (BPD), and others. These defects are caused by deviations in the arrangement of atoms at the atomic level. SiC crystals may also have macroscopic dislocations, like Si or C inclusions, micropipe, hexagonal voids, polymorphs, etc. These dislocations are typically large in size.

Isostatic graphite is a type of graphite with an ultra-fine grain. It is used for applications where the mechanical properties of other fine-grained graphites are inadequate.

The Silicon Carbide (SiC) production process encompasses the preparation of substrate and epitaxy from the materials side, followed by chip design and manufacturing, device packaging, and finally, distribution to downstream application markets. Among these stages, substrate material processing is the most challenging aspect of the SiC industry. SiC substrates are both hard and brittle, making cutting, grinding, and polishing extremely difficult. This increases the likelihood of defects during processing and reduces the yield rate. Currently, major international SiC manufacturers are planning to transition from 6-inch to 8-inch SiC wafers. Overcoming the challenges associated with 8-inch substrates has become a critical benchmark for the SiC industry. This article will introduce the key parameters of SiC substrates.

The most basic stage of all processes is the oxidation process. The oxidation process is to place the silicon wafer in an atmosphere of oxidants such as oxygen or water vapor for high-temperature heat treatment (800~1200℃), and a chemical reaction occurs on the surface of the silicon wafer to form an oxide film (SiO2 film).

Gallium Nitride (GaN) epitaxial wafer growth is a complex process, often utilizing a two-step method. This method involves several critical stages, including high-temperature baking, buffer layer growth, recrystallization, and annealing. By meticulously controlling the temperature throughout these stages, the two-step growth method effectively prevents wafer warping caused by lattice mismatch or stress, making it the predominant fabrication method for GaN epitaxial wafers globally.