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The current third-generation semiconductors are primarily based on Silicon Carbide, with substrates accounting for 47% of device costs, and epitaxy accounting for 23%, totaling approximately 70% and forming the most crucial part of the SiC device manufacturing industry.

To meet the demands for high performance and low power consumption in the realm of modern semiconductor technology, SiGe (Silicon Germanium) has emerged as a composite material of choice in semiconductor chip manufacturing due to its unique physical and electrical properties.

The Silicon Carbide (SiC) production process encompasses the preparation of substrate and epitaxy from the materials side, followed by chip design and manufacturing, device packaging, and finally, distribution to downstream application markets. Among these stages, substrate material processing is the most challenging aspect of the SiC industry. SiC substrates are both hard and brittle, making cutting, grinding, and polishing extremely difficult. This increases the likelihood of defects during processing and reduces the yield rate. Currently, major international SiC manufacturers are planning to transition from 6-inch to 8-inch SiC wafers. Overcoming the challenges associated with 8-inch substrates has become a critical benchmark for the SiC industry. This article will introduce the key parameters of SiC substrates.

Gallium oxide (Ga2O3) has emerged as a promising material for various applications, particularly in power devices and radio frequency (RF) devices. In this article, we explore the key opportunities and target markets for gallium oxide in these domains.

The tray (base) that supports SiC wafers, also known as a "susceptor," is a core component of semiconductor manufacturing equipment. And what exactly is this susceptor that carries the wafers?

As technology nodes continue to shrink, the formation of ultra-shallow junctions presents significant challenges. Thermal annealing processes including Rapid thermal annealing (RTA) and flash lamp annealing (FLA) are vital techniques that maintain high impurity activation rates while minimizing diffusion, ensuring optimal device performance.