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Both are N-type semiconductors, but what's the difference between arsenic and phosphorus doping in single-crystal silicon? In single-crystal silicon, arsenic (As) and phosphorus (P) are both commonly used N-type dopants (pentavalent elements that provide free electrons). However, due to differences in atomic structure, physical properties, and processing characteristics, their doping effects and application scenarios differ significantly.

Etching is an essential process in semiconductor manufacturing. This process can be categorized into two types: dry etching and wet etching. Each technique has its own advantages and limitations, making it crucial to understand the differences between them. So, how do you choose the best etching method? What are the pros and cons of dry etching and wet etching?

Semicorex offers high-quality thermal insulation felt and glass-like carbon coating.

Currently, many semiconductor devices employ mesa device structures, which are predominantly created through two types of etching: wet etching and dry etching. While the simple and rapid wet etching plays a significant role in semiconductor device fabrication, it has inherent drawbacks such as isotropic etching and poor uniformity, which result in limited control when transferring small-sized patterns. Dry etching, however, with its high anisotropy, good uniformity, and repeatability, has become prominent in semiconductor device fabrication processes. The term “dry etching” broadly refers to any non-wet etching technology used for removing surface materials and transferring micro and nano patterns, including laser etching, plasma etching, and chemical vapor etching. The dry etching discussed in this text specifically pertains to the narrow application of processes using plasma discharge—either physical or chemical—to modify material surfaces.

Currently, most SiC substrate manufacturers use a new crucible thermal field process design with porous graphite cylinders: placing high-purity SiC particle raw materials between the graphite crucible wall and the porous graphite cylinder, while deepening the entire crucible and increasing the crucible diameter.

SiC substrate can have microscopic defects, such as Threading Screw Dislocation (TSD), Threading Edge Dislocation (TED), Base Plane Dislocation (BPD), and others. These defects are caused by deviations in the arrangement of atoms at the atomic level. SiC crystals may also have macroscopic dislocations, like Si or C inclusions, micropipe, hexagonal voids, polymorphs, etc. These dislocations are typically large in size.