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The liquid phase method is closer to the thermodynamic equilibrium conditions and is able to grow SiC crystals with better quality.

As the world looks for new opportunities in semiconductors, gallium nitride continues to stand out as a potential candidate for future power and RF applications. However, for all the benefits it offers, it still faces a major challenge; there are no P-type (P-type) products. Why is GaN touted as the next major semiconductor material, why is the lack of P-type GaN devices a major drawback, and what does this mean for future designs?

Silicon carbide has a large number of applications in emerging industries and traditional industries. At present, the global semiconductor market has exceeded 100 billion yuan. It is expected that by 2025, the global sales of semiconductor manufacturing materials will reach 39.5 billion US dollars, of which the silicon carbide semiconductor market is expected to reach a market size of 2.5 billion US dollars in 2025. At the same time, silicon carbide is still the material with the best application performance in traditional ceramics, refractory, high temperature, grinding and other fields.

The Silicon Carbide (SiC) production process encompasses the preparation of substrate and epitaxy from the materials side, followed by chip design and manufacturing, device packaging, and finally, distribution to downstream application markets. Among these stages, substrate material processing is the most challenging aspect of the SiC industry. SiC substrates are both hard and brittle, making cutting, grinding, and polishing extremely difficult. This increases the likelihood of defects during processing and reduces the yield rate. Currently, major international SiC manufacturers are planning to transition from 6-inch to 8-inch SiC wafers. Overcoming the challenges associated with 8-inch substrates has become a critical benchmark for the SiC industry. This article will introduce the key parameters of SiC substrates.

Silicon Carbide (SiC) single crystals are primarily produced using the sublimation method. After removing the crystal from the crucible, several intricate processing steps are required to create usable wafers.

To achieve the high-quality requirements of IC chip circuit processes with line widths smaller than 0.13μm to 28nm for 300mm diameter silicon polishing wafers, it is essential to minimize contamination from impurities, such as metal ions, on the wafer's surface.