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Silicon carbide (SiC) ceramic is a type of advanced ceramic material known for its exceptional properties and wide range of applications. It is composed of silicon (Si) and carbon (C) atoms arranged in a crystal lattice structure, resulting in a hard and strong material with excellent thermal and electrical conductivity.

Recently, the semiconductor industry has continued to pay increasing attention to Gallium Nitride (GaN) technology. Due to its excellent electronic properties, Gallium Nitride devices have important applications in many high-tech fields:

Currently, many semiconductor devices employ mesa device structures, which are predominantly created through two types of etching: wet etching and dry etching. While the simple and rapid wet etching plays a significant role in semiconductor device fabrication, it has inherent drawbacks such as isotropic etching and poor uniformity, which result in limited control when transferring small-sized patterns. Dry etching, however, with its high anisotropy, good uniformity, and repeatability, has become prominent in semiconductor device fabrication processes. The term “dry etching” broadly refers to any non-wet etching technology used for removing surface materials and transferring micro and nano patterns, including laser etching, plasma etching, and chemical vapor etching. The dry etching discussed in this text specifically pertains to the narrow application of processes using plasma discharge—either physical or chemical—to modify material surfaces.

In the field of single crystal growth, the temperature distribution within the crystal growth furnace plays a critical role. This temperature distribution, commonly referred to as the thermal field, is a vital factor that influences the quality and characteristics of the crystal being grown. The thermal field can be categorized into two types: static and dynamic.

In semiconductor manufacturing, the precision and stability of the etching process are paramount. One critical factor in achieving high-quality etching is ensuring that wafers are perfectly flat on the tray during the process.

The wafer notch is a V-shaped or U-shaped groove on the edge of a semiconductor wafer. Far from being a defect incurred during the manufacturing process, it is the critical structural marker that was intentionally designed, whose core function lies in enabling precise positioning and orientation identification of the wafer. Wafer flat was used as the orientation marking in the early stages of wafer technology development. However, as wafer sizes gradually increased, the flat-edge design occupied more effective area, thus being gradually replaced by the more compact notch.