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  • Reviews

  • CVD process for SiC wafer epitaxy

    The CVD process for SiC wafer epitaxy involves the deposition of SiC films onto a SiC substrate using a gas-phase reaction. The SiC precursor gases, typically methyltrichlorosilane (MTS) and ethylene (C2H4), are introduced into a reaction chamber where the SiC substrate is heated to a high temperature (usually between 1400 and 1600 degrees Celsius) under a controlled atmosphere of hydrogen (H2).

  • What is porous graphite?

    Porous graphite, also known as porous carbon or porous graphite material, is a graphite form that has been specially engineered to have an interconnected network of pores or voids within its structure.

  • What is C/C composite?

    C/C composite is a carbon-carbon composite material made of carbon fibers as reinforcement and carbon as matrix through processing and carbonization, with excellent mechanical and high-temperature resistance properties. The material was initially used in aerospace and special fields, and with the maturity of the technology, it has been gradually used in photovoltaic, automotive, lithium battery, medical devices and other fields.

  • Method for preparing SiC powder

    Silicon carbide (SiC) is an inorganic substance. The amount of naturally occurring silicon carbide is very small. It is a rare mineral and is called moissanite. Silicon carbide used in industrial production is mostly artificially synthesized.

  • Introduction to the Silicon Carbide Ion Implantation and Annealing Process

    In traditional silicon power device fabrication, high-temperature diffusion and ion implantation stand as the primary methods for dopant control, each with its advantages and disadvantages. Typically, high-temperature diffusion is characterized by its simplicity, cost-effectiveness, isotropic dopant distribution profiles, and lower introduction of lattice damage. Conversely, ion implantation, though complex and costly, enables precise independent control over dopant concentration and depth but introduces a significant number of point defects and extended defects into the substrate.

  • What is CMP Process

    In semiconductor manufacturing, atomic-level flatness is usually used to describe the global flatness of the wafer, with the unit of nanometers (nm).

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