China Ceramic Materials Manufacturers, Suppliers, Factory

By 2027, solar photovoltaic (PV) will overtake coal as the world's largest installed capacity. The cumulative installed capacity of solar PV nearly triples in our forecast, growing by nearly 1,500 gigawatts over this period, and will surpass natural gas by 2026 and coal by 2027.

Currently, many semiconductor devices employ mesa device structures, which are predominantly created through two types of etching: wet etching and dry etching. While the simple and rapid wet etching plays a significant role in semiconductor device fabrication, it has inherent drawbacks such as isotropic etching and poor uniformity, which result in limited control when transferring small-sized patterns. Dry etching, however, with its high anisotropy, good uniformity, and repeatability, has become prominent in semiconductor device fabrication processes. The term “dry etching” broadly refers to any non-wet etching technology used for removing surface materials and transferring micro and nano patterns, including laser etching, plasma etching, and chemical vapor etching. The dry etching discussed in this text specifically pertains to the narrow application of processes using plasma discharge—either physical or chemical—to modify material surfaces.

The process of silicon carbide substrate is complex and difficult to manufacture. SiC substrate occupies the main value of the industry chain, accounting for 47%. It is expected that with the expansion of production capacity and the improvement of yield in the future, it is expected to drop to 30%.

​As the world searches for new opportunities in the semiconductor field, Gallium Nitride (GaN) continues to stand out as a potential candidate for future power and RF applications. However, despite its numerous benefits, GaN faces a significant challenge: the absence of P-type products. Why is GaN hailed as the next major semiconductor material, why is the lack of P-type GaN devices a critical drawback, and what does this mean for future designs?

To achieve the high-quality requirements of IC chip circuit processes with line widths smaller than 0.13μm to 28nm for 300mm diameter silicon polishing wafers, it is essential to minimize contamination from impurities, such as metal ions, on the wafer's surface.