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SiC substrate can have microscopic defects, such as Threading Screw Dislocation (TSD), Threading Edge Dislocation (TED), Base Plane Dislocation (BPD), and others. These defects are caused by deviations in the arrangement of atoms at the atomic level. SiC crystals may also have macroscopic dislocations, like Si or C inclusions, micropipe, hexagonal voids, polymorphs, etc. These dislocations are typically large in size.

Within the silicon carbide (SiC) industry chain, substrate suppliers hold significant leverage, primarily due to value distribution. SiC substrates account for 47% of the total value, followed by epitaxial layers at 23%, while device design and manufacturing constitute the remaining 30%. This inverted value chain stems from the high technological barriers inherent to substrate and epitaxial layer production. Three major challenges plague SiC substrate growth: stringent growth conditions, slow growth rates, and demanding crystallographic requirements. These complexities contribute to increased processing difficulty, ultimately resulting in low product yields and high costs. Furthermore, the epitaxial layer’s thickness and doping concentration are critical parameters directly impacting the final device performance.

According to reports from German media, U.S. chip manufacturer Wolfspeed is pausing its plans to build a semiconductor plant in Germany.

Semiconductors are materials whose electrical conductivity at room temperature lies between that of insulators and conductors. By introducing impurities, a process known as doping, these materials can become conductors.